28 search results - page 2 / 6 » High Level Synthesis Of Multi-Precision Data Flow Graphs |
ERSA
2009
13 years 2 months ago
2009
- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
ISSS
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
ISSS
1997
IEEE
13 years 9 months ago
1997
IEEE
Integer Linear Programming ILP is commonly used in high level and system level synthesis. It is an NP-Complete problem in general cases . There exists some tools that give an o...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...