88 search results - page 2 / 18 » High Level Synthesis from Sim-nML Processor Models |
APCSAC
2001
IEEE
13 years 8 months ago
2001
IEEE
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- Most image processing applications are computationally intensive and data intensive. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these a...
MEMOCODE
2007
IEEE
13 years 11 months ago
2007
IEEE
Orthogonal Frequency-Division Multiplexing (OFDM) has become the preferred modulation scheme for both broadband and high bitrate digital wireless protocols because of its spectral...
RSP
2005
IEEE
13 years 10 months ago
2005
IEEE
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...