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» High level synthesis for reconfigurable datapath structures
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ASAP
1996
IEEE
145views Hardware» more  ASAP 1996»
13 years 9 months ago
A Synthesis System For Bus-Based Wavefront Array Architectures
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...
Reiner W. Hartenstein, Jürgen Becker, Michael...
ICCAD
1993
IEEE
97views Hardware» more  ICCAD 1993»
13 years 9 months ago
High level synthesis for reconfigurable datapath structures
Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
ASPDAC
1995
ACM
116views Hardware» more  ASPDAC 1995»
13 years 8 months ago
A datapath synthesis system for the reconfigurable datapath architecture
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...
Reiner W. Hartenstein, Rainer Kress
ICES
2003
Springer
151views Hardware» more  ICES 2003»
13 years 10 months ago
Using Genetic Programming and High Level Synthesis to Design Optimized Datapath
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...
Sérgio G. Araújo, Antônio C. M...
ICCD
1992
IEEE
126views Hardware» more  ICCD 1992»
13 years 9 months ago
High-Level State Machine Specification and Synthesis
Current synthesis methodologies based on hardwaredescription languages focus mainly on two distinct levels: behavior and register-transfer levels. In many practical cases, however...
Andreas Kuehlmann, Reinaldo A. Bergamaschi