10 search results - page 2 / 2 » High-Performance Carry Chains for FPGAs |
FPL
2009
Springer
13 years 10 months ago
2009
Springer
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
ARVLSI
2001
IEEE
13 years 9 months ago
2001
IEEE
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
FPGA
2008
ACM
13 years 7 months ago
2008
ACM
Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose pr...
ICMCS
2007
IEEE
13 years 12 months ago
2007
IEEE
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...