140 search results - page 2 / 28 » High-level design for asynchronous logic |
ICVS
2003
Springer
13 years 10 months ago
2003
Springer
This paper explores high-level scene interpretation with logic-based conceptual models. The main interest is in aggregates which describe interesting co-occurrences of physical obj...
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
EVOW
2001
Springer
13 years 9 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
Symmetric input identification is an important technique in logic synthesis. Previous approaches deal with this problem by building BDDs and developing algorithms to determine symm...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...