12 search results - page 2 / 3 » High-level power analysis for on-chip networks |
DSD
2006
IEEE
13 years 11 months ago
2006
IEEE
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
INTEGRATION
2008
13 years 5 months ago
2008
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...