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TCAD
2010
121views more  TCAD 2010»
12 years 12 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
EVOW
2001
Springer
13 years 9 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
DSD
2006
IEEE
93views Hardware» more  DSD 2006»
13 years 11 months ago
High-Level Decision Diagram based Fault Models for Targeting FSMs
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...
Jaan Raik, Raimund Ubar, Taavi Viilukas
TVLSI
2008
140views more  TVLSI 2008»
13 years 5 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
CVPR
2003
IEEE
14 years 7 months ago
Expectation Grammars: Leveraging High-Level Expectations for Activity Recognition
Video-based recognition and prediction of a temporally extended activity can benefit from a detailed description of high-level expectations about the activity. Stochastic grammars...
David Minnen, Irfan A. Essa, Thad Starner