54 search results - page 4 / 11 » High-level synthesis scheduling and allocation using genetic... |
ISQED
2005
IEEE
13 years 11 months ago
2005
IEEE
As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for hig...
VLSID
1996
IEEE
13 years 10 months ago
1996
IEEE
A technique for allocatzon and binding for data path synthesis (DPS) using a Genetic Algorithm (GA) approach has been developed. The proposed genetic algorithm uses a non-conventi...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of fun...
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
GECCO
2005
Springer
13 years 11 months ago
2005
Springer
Optimization problems such as resource allocation, job-shop scheduling, equipment utilization and process scheduling occur in a broad range of processing industries. This paper pr...