38 search results - page 8 / 8 » High-level test synthesis for delay fault testability |
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...
DT
2000
13 years 5 months ago
2000
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...