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    CODES
    2003
    IEEE
    170views Software Engineering» more  CODES 2003»
    A fast parallel reed-solomon decoder on a reconfigurable architecture
    13 years 10 months ago
    A fast parallel reed-solomon decoder on a reconfigurable architecture
    Download  www.cecs.uci.edu
    This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
    Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
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    SIGCOMM
    1990
    ACM
    100views Communications» more  SIGCOMM 1990»
    Reliable Broadband Communication Using a Burst Erasure Correcting Code
    13 years 9 months ago
    Reliable Broadband Communication Using a Burst Erasure Correcting Code
    Download  www.cs.iastate.edu
    Traditionally, a transport protocol corrects errors in a computer communication network using a simple ARQ protocol. With the arrival of broadband networks, forward error correcti...
    Anthony J. McAuley
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    ISVLSI
    2005
    IEEE
    115views VLSI» more  ISVLSI 2005»
    High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization
    13 years 11 months ago
    High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization
    Download  www.see.ed.ac.uk
    The authors present a turbo soft-in soft-out (SISO) decoder based on Max-Log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique...
    J. H. Han, Ahmet T. Erdogan, Tughrul Arslan
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    TSP
    2008
    158views more  TSP 2008»
    High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform
    13 years 5 months ago
    High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform
    Download  www.tc.umn.edu
    This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D D...
    Chao Cheng, Keshab K. Parhi
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    ARVLSI
    1997
    IEEE
    104views VLSI» more  ARVLSI 1997»
    A High-Speed Asynchronous Decompression Circuit for Embedded Processors
    13 years 9 months ago
    A High-Speed Asynchronous Decompression Circuit for Embedded Processors
    Download  www.cs.columbia.edu
    This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
    Martin Benes, Andrew Wolfe, Steven M. Nowick
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