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CASES
2006
ACM
13 years 11 months ago
Automatic performance model construction for the fast software exploration of new hardware designs
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
John Cavazos, Christophe Dubach, Felix V. Agakov, ...
TVLSI
2008
187views more  TVLSI 2008»
13 years 5 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
DSN
2008
IEEE
13 years 11 months ago
A characterization of instruction-level error derating and its implications for error detection
In this work, we characterize a significant source of software derating that we call instruction-level derating. Instruction-level derating encompasses the mechanisms by which co...
Jeffrey J. Cook, Craig B. Zilles
COMPSAC
2002
IEEE
13 years 10 months ago
Using RAIC for Dependable On-line Upgrading of Distributed Systems
Redundant Arrays of Independent Components (RAIC) is a technology that uses groups of similar or identical distributed components to provide dependable services [1,2,3]. RAIC allo...
Chang Liu, Debra J. Richardson
CHES
2000
Springer
97views Cryptology» more  CHES 2000»
13 years 8 months ago
Software-Hardware Trade-Offs: Application to A5/1 Cryptanalysis
This paper shows how a well-balanced trade-off between a generic workstation and dumb but fast reconfigurable hardware can lead to a more efficient implementation of a cryptanalysi...
Thomas Pornin, Jacques Stern