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DAC
2009
ACM
14 years 6 months ago
ILP-based pin-count aware design methodology for microfluidic biochips
Digital microfluidic biochips have emerged as a popular alternative for laboratory experiments. To make the biochip feasible for practical applications, pin-count reduction is a k...
Cliff Chiung-Yu Lin, Yao-Wen Chang
DAC
2002
ACM
14 years 6 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
13 years 11 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...