43 search results - page 2 / 9 » Hybrid Cache Architecture for High Speed Packet Processing |
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
JSAC
2006
13 years 4 months ago
2006
The ability to inspect both packet headers and payloads to identify attack signatures makes network intrusion detection system (NIDS) a promising approach to protect Internet syste...
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...