128 search results - page 1 / 26 » ILP-based optimization of sequential circuits for low power |
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
ARVLSI
1995
IEEE
13 years 8 months ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
The power consumption of a sequential circuit can be reduced by decomposing it into subcircuits which can be turned off when inactive. Power can also be reduced by careful state e...
DFT
1999
IEEE
13 years 9 months ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
EVOW
1999
Springer
13 years 9 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...