111 search results - page 1 / 23 » IPR: An Integrated Placement and Routing Algorithm |
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
A block-level placement and routing scheme called Fishbone is presented. The routing uses a two-layer spine topology. The pin locations are configurable and restricted to certain ...
ISPD
2005
ACM
13 years 10 months ago
2005
ACM
In this paper, we present a hierarchical ratio partitioning based placement algorithm for large-scale mixed-size designs. The placement algorithm consists of three steps: global p...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
ISPD
2012
ACM
12 years 8 days ago
2012
ACM
As technology scales and frequency increases, a new design style is emerging, referred to as hybrid designs, which contain a mixture of random logic and datapath standard cell com...