155 search results - page 1 / 31 » ITOP: integrating timing optimization within placement |
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
Abstract— Regular structures are present in many types of circuits. If this structure can be identified and utilized, performance can be improved dramatically. In this paper, we...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations a...
MASCOTS
2003
13 years 6 months ago
2003
The Web proxy cache placement problem is often formulated as a classical optimization problem: place N proxies within an internetwork so as to minimize the average user response t...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...