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» Identification and Test Generation for Primitive Faults
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ITC
1996
IEEE
78views Hardware» more  ITC 1996»
13 years 9 months ago
Identification and Test Generation for Primitive Faults
Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakrad...
ICCAD
1998
IEEE
116views Hardware» more  ICCAD 1998»
13 years 9 months ago
On primitive fault test generation in non-scan sequential circuits
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
Ramesh C. Tekumalla, Premachandran R. Menon
ICCAD
1991
IEEE
135views Hardware» more  ICCAD 1991»
13 years 8 months ago
DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits
This paper presents an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to ...
Torsten Grüning, Udo Mahlstedt, Hartmut Koopm...
DATE
2006
IEEE
98views Hardware» more  DATE 2006»
13 years 11 months ago
Test generation for combinational quantum cellular automata (QCA) circuits
— In this paper, we present a test generation framework for testing of quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted significant recent at...
Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
ASPDAC
1998
ACM
65views Hardware» more  ASPDAC 1998»
13 years 9 months ago
A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
Miyako Tandai, Takao Shinsha