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VLSID
2007
IEEE
103views VLSI» more  VLSID 2007»
14 years 5 months ago
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
Abstract-- This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variation...
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopala...
GLVLSI
2006
IEEE
101views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance
Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include interand intra-die variations of geometries, as well as...
Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, ...
CISIS
2009
IEEE
13 years 11 months ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
Francisco Gilabert Villamón, Daniele Ludovi...
DFT
1998
IEEE
84views VLSI» more  DFT 1998»
13 years 9 months ago
Process Variations and their Impact on Circuit Operation
The statistical variations in electrical parameters, such as transistor gain factors and interconnect resistances, due to variations in the manufacturing process are studied using...
Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep...
GLVLSI
2006
IEEE
143views VLSI» more  GLVLSI 2006»
13 years 11 months ago
SACI: statistical static timing analysis of coupled interconnects
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, A...