30 search results - page 3 / 6 » Impact of Sharing-Based Thread Placement on Multithreaded Ar... |
IPPS
2003
IEEE
13 years 10 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
PPOPP
2010
ACM
13 years 11 months ago
2010
ACM
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
MICRO
1998
IEEE
13 years 9 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
ISPASS
2007
IEEE
13 years 11 months ago
2007
IEEE
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...