419 search results - page 1 / 84 » Impact of Technology Scaling in the Clock System Power |
ISVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic VDD...
ISCA
2002
IEEE
13 years 9 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...