Sciweavers

15 search results - page 2 / 3
» Impact of Technology and Voltage Scaling on the Soft Error S...
Sort
View
DAC
2004
ACM
13 years 8 months ago
Leakage in nano-scale technologies: mechanisms, impact and design considerations
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, K...
MICRO
2008
IEEE
208views Hardware» more  MICRO 2008»
13 years 11 months ago
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
Wangyuan Zhang, Tao Li
DAC
2006
ACM
14 years 5 months ago
MARS-C: modeling and reduction of soft errors in combinational circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
Natasa Miskov-Zivanov, Diana Marculescu
GLVLSI
2006
IEEE
193views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
DATE
2008
IEEE
119views Hardware» more  DATE 2008»
13 years 11 months ago
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
Drew C. Ness, David J. Lilja