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» Impact of strain on the design of low-power high-speed circu...
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GLVLSI
2003
IEEE
310views VLSI» more  GLVLSI 2003»
13 years 11 months ago
54x54-bit radix-4 multiplier based on modified booth algorithm
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...
DELTA
2006
IEEE
13 years 11 months ago
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method
In high speed digital circuits, the inductive effect is more dominant compared to capacitive effect. In particular, as the technology is shrinking, the spacing between interconnec...
K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srini...
ICC
2007
IEEE
143views Communications» more  ICC 2007»
14 years 2 days ago
Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications
Abstract— Ultra-wideband (UWB) impulse radio is a promising technique for low-power bio-medical communication systems. While a range of analog and digital UWB architectures exist...
Andrew Fort, Mike Chen, Robert W. Brodersen, Claud...
ICDCS
1997
IEEE
13 years 10 months ago
Effect of Connection Rerouting on Application Performance in Mobile Networks
—The increasing deployment of wireless access technology, along with the emergence of high speed integrated service networks, such as ATM, promises to provide mobile users with u...
Partho Pratim Mishra, Mani B. Srivastava
MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
14 years 12 days ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002