54x54-bit radix-4 multiplier based on modified booth algorithm

In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 28-2, 27-2, …, and 10-2 compressors, and XOR based adder are proposed. While the whole design is coded in Verilog-HDL language and implemented through commercially available EDA tool chain, the implementation gives comparable results to full custom designs [1][2]. Realistic simulations using extracted timing parameters from the layout show that the propagation time of a critical path is 3.25ns at 2.5V on a 0.18um process technology, which is almost 21% faster than the conventional multiplier [2]. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles – Advanced technologies, Microprocessors and microcomputers, Algorithms implemented in hardware. General Terms Algorithms, Performance, Design. Keywords Multiplier, Booth encoder, Wallace tree, Compressor, Adder

• Type: Conference
• Year: 2003
• Where: GLVLSI
• Authors: Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-seog Choi
• Keywords: Booth Encoder, GLVLSI 2003, Optimized Booth Encoder, VLSI, XOR Based Adder