15 search results - page 2 / 3 » Implementation of a programmable array processor architectur... |
WOB
2004
13 years 6 months ago
2004
ABSTRACT. Reconfigurable systolic arrays can be adapted to efficiently resolve a wide spectrum of computational problems; parallelism is naturally explored in systolic arrays and r...
CF
2009
ACM
13 years 11 months ago
2009
ACM
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
FPGA
2001
ACM
13 years 9 months ago
2001
ACM
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
CSB
2005
IEEE
13 years 10 months ago
2005
IEEE
This work presents the development of algorithms for approximate string matching using parallel methods. It intends to do the maximum of molecular sequences comparisons per unity ...
ANCS
2005
ACM
13 years 10 months ago
2005
ACM
This paper presents a hardware architecture for highly efficient intrusion detection systems. In addition, a software tool for automatically generating the hardware is presented....