857 search results - page 1 / 172 » Implementing a STARI chip |
ICCD
1995
IEEE
13 years 8 months ago
1995
IEEE
STARI is a high-speed signaling technique that uses both synchronous and self-timed circuits. To demonstrate STARI, a chip has been fabricated using the MOSIS 2 CMOS process. In a...
ASPDAC
2010
ACM
13 years 3 months ago
2010
ACM
ECRTS
2009
IEEE
13 years 3 months ago
2009
IEEE
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
TCAD
2010
13 years 4 hour ago
2010
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient netwo...
JSA
2010
13 years 2 days ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...