141 search results - page 1 / 29 » Implications of technology scaling on leakage reduction tech... |
DAC
2003
ACM
14 years 5 months ago
2003
ACM
The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limit...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage r...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
DAC
2004
ACM
13 years 8 months ago
2004
ACM
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...