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» Imprecise Exceptions in Distributed Parallel Components
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EUROPAR
2004
Springer
12 years 3 months ago
Imprecise Exceptions in Distributed Parallel Components
Abstract. Modern microprocessors have sacrificed the exactness of exceptions for improved performance long ago. This is a side effect of reordering instructions so that the micropr...
Kostadin Damevski, Steven G. Parker
ICDCS
1998
IEEE
12 years 3 months ago
Flexible Exception Handling in the OPERA Process Support System
Exceptions are one of the most pervasive problems in process support systems. In installations expected to handle a large number of processes, having exceptions is bound to be a n...
Claus Hagen, Gustavo Alonso
MIDDLEWARE
2009
Springer
12 years 6 months ago
DR-OSGi: Hardening Distributed Components with Network Volatility Resiliency
Abstract. Because middleware abstractions remove the need for lowlevel network programming, modern distributed component systems expose network volatility (i.e., frequent but inter...
Young-Woo Kwon, Eli Tilevich, Taweesup Apiwattanap...
HPCA
1996
IEEE
12 years 3 months ago
Register File Design Considerations in Dynamically Scheduled Processors
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
Keith I. Farkas, Norman P. Jouppi, Paul Chow
MICRO
2008
IEEE
107views Hardware» more  MICRO 2008»
12 years 6 months ago
A distributed processor state management architecture for large-window processors
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
Isidro Gonzalez, Marco Galluzzi, Alexander V. Veid...
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