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» Improve Chip Pin Performance Using Optical Interconnects
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ICIP
2001
IEEE
14 years 7 months ago
Optical flow estimation using high frame rate sequences
Gradient-based optical flow estimation methods such as LucasKanade method work well for scenes with small displacements but fail when objects move with large displacements. Hierar...
SukHwan Lim, Abbas El Gamal
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 4 days ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
NOCS
2008
IEEE
14 years 4 days ago
Reducing the Interconnection Network Cost of Chip Multiprocessors
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
Pablo Abad, Valentin Puente, José-Án...
MICRO
2006
IEEE
117views Hardware» more  MICRO 2006»
13 years 11 months ago
Coherence Ordering for Ring-based Chip Multiprocessors
Ring interconnects may be an attractive solution for future chip multiprocessors because they can enable faster links than buses and simpler switches than arbitrary switched inter...
Michael R. Marty, Mark D. Hill
SLIP
2009
ACM
14 years 7 days ago
Prediction of high-performance on-chip global interconnection
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin...