28 search results - page 2 / 6 » Improved Delay and Current Models for Estimating Maximum Cur... |
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
ICCAD
1997
IEEE
13 years 10 months ago
1997
IEEE
Maximum instantaneous power in VLSI circuits has a great impact on circuit's reliability and the design of power and ground lines. To synthesizehighlyreliablesystems,accurate...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...