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» Improved global routing through congestion estimation
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TCAD
2002
73views more  TCAD 2002»
13 years 4 months ago
A timing-constrained simultaneous global routing algorithm
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar
HPCA
2008
IEEE
14 years 5 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
TCAD
2010
112views more  TCAD 2010»
13 years 2 hour ago
Multilayer Global Routing With Via and Wire Capacity Considerations
Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a sim...
Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang
ICCAD
2010
IEEE
176views Hardware» more  ICCAD 2010»
13 years 2 months ago
An auction based pre-processing technique to determine detour in global routing
Global Routing has been a traditional EDA problem. It has congestion elimination as the first and foremost priority. Despite of the recent development for popular rip-up and rerout...
Yue Xu, Chris Chu
ICCAD
2000
IEEE
91views Hardware» more  ICCAD 2000»
13 years 9 months ago
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar