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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
13 years 11 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
TCAD
2010
154views more  TCAD 2010»
13 years 8 days ago
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style
In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the sa...
Fu-Wei Chen, Yi-Yu Liu
HPCA
2008
IEEE
14 years 6 months ago
Single-level integrity and confidentiality protection for distributed shared memory multiprocessors
Multiprocessor computer systems are currently widely used in commercial settings to run critical applications. These applications often operate on sensitive data such as customer ...
Brian Rogers, Chenyu Yan, Siddhartha Chhabra, Milo...
DAC
2005
ACM
14 years 6 months ago
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 9 months ago
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...
Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh ...