Sciweavers

16 search results - page 2 / 4
» Improved performance and variation modelling for hierarchica...
Sort
View
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
13 years 11 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
ISQED
2007
IEEE
150views Hardware» more  ISQED 2007»
13 years 11 months ago
A Design Methodology for Matching Improvement in Bandgap References
Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significa...
Juan Pablo Martinez Brito, Hamilton Klimach, Sergi...
ICCAD
2006
IEEE
106views Hardware» more  ICCAD 2006»
14 years 1 months ago
Wire density driven global routing for CMP variation and timing
In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compac...
Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
ISPD
2010
ACM
205views Hardware» more  ISPD 2010»
13 years 11 months ago
Total sensitivity based dfm optimization of standard library cells
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
Yongchan Ban, Savithri Sundareswaran, David Z. Pan
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
13 years 10 months ago
Vectorless Analysis of Supply Noise Induced Delay Variation
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...