4 search results - page 1 / 1 » Improvement of the Fault Coverage of the Pseudo-Random Phase... |
DSD
2005
IEEE
13 years 6 months ago
2005
IEEE
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
DSD
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
VTS
2006
IEEE
13 years 11 months ago
2006
IEEE
We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop stro...
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
: This project involves the design of a CMOS RF RMS Detector that converts the RMS voltage amplitude of an RF signal to a DC voltage. Its high input impedance and small area make i...