38 search results - page 1 / 8 » Improving FPGA Performance and Area Using an Adaptive Logic ... |
FPL
2004
Springer
13 years 10 months ago
2004
Springer
This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay...
FPGA
2008
ACM
13 years 6 months ago
2008
ACM
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
TVLSI
2010
12 years 11 months ago
2010
The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP...
FPGA
1995
ACM
13 years 8 months ago
1995
ACM
In this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization in the mapping process by computing min-cost min-height...