328 search results - page 3 / 66 » Improving Performance of Small On-Chip Instruction Caches |
MICRO
2010
IEEE
13 years 3 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
NOCS
2008
IEEE
14 years 4 days ago
2008
IEEE
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
ISCA
2008
IEEE
14 years 5 days ago
2008
IEEE
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...
HPCA
1999
IEEE
13 years 10 months ago
1999
IEEE
We propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior o...
CASES
2007
ACM
13 years 9 months ago
2007
ACM
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...