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IEEEPACT
2006
IEEE
13 years 11 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
GPC
2008
Springer
13 years 6 months ago
Using Moldability to Improve Scheduling Performance of Parallel Jobs on Computational Grid
In a computational grid environment, a common practice is try to allocate an entire parallel job onto a single participating site. Sometimes a parallel job, upon its submission, ca...
Kuo-Chan Huang, Po-Chi Shih, Yeh-Ching Chung
CODES
2011
IEEE
12 years 5 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
13 years 11 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
ESWA
2008
219views more  ESWA 2008»
13 years 5 months ago
Business intelligence approach to supporting strategy-making of ISP service management
The recent deregulation of telecommunication industry by the Taiwanese government has brought about the acute competition for Internet Service Providers (ISP). Taiwan's ISP i...
Sheng-Tun Li, Li-Yen Shue, Shu-Fen Lee