11 search results - page 2 / 3 » Improving the Proportion of At-Speed Tests in Scan BIST |
ATS
2004
IEEE
13 years 9 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
IOLTS
2006
IEEE
13 years 11 months ago
2006
IEEE
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
— We examine an abstract formulation of BIST diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vector...