Low Power BIST with Smoother and Scan-Chain Reorder

In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption during scan testing, while a group-based greedy algorithm is employed for the scan-chain reorder in order to improve the fault coverage. The reordering algorithm is very efficient in terms of computation time, and the routing length of the reordered scan-chain is comparable to result given by commercial tools. Experimental results of ISCAS'89 benchmarks show that the fault coverage achieved by the 2-bit and 3-bit smoothers are similar to previous methods with the same test lengths. The reduction in average power consumption is 60.06% with a 2-bit smoother and 85.4% with a 3-bit smoother. These results are much better than those achieved by previous methods.

• Type: Conference
• Year: 2004
• Where: ATS
• Authors: Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu
• Keywords: 3-bit Smoother, ATS 2004, Average Power Consumption, Fault Coverage, Hardware