24 search results - page 2 / 5 » Improving the Throughput of a Pipeline by Insertion of Delay... |
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
HPCA
2001
IEEE
14 years 5 months ago
2001
IEEE
This paper introduces a router delay model that accurately models key aspects of modern routers. The model accounts for the pipelined nature of contemporary routers, the specific ...
ICC
2008
IEEE
13 years 11 months ago
2008
IEEE
— Cooperative relaying has recently been recognized as an alternative to MIMO in a typical multi cellular environment. Inserting random delays at the non-regenerative fixed rela...
ICCD
2000
IEEE
14 years 2 months ago
2000
IEEE
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...