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» Incremental Signaling Pathway Modeling by Data Integration
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IOLTS
2003
IEEE
133views Hardware» more  IOLTS 2003»
13 years 11 months ago
Power Consumption of Fault Tolerant Codes: the Active Elements
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
Daniele Rossi, Steven V. E. S. van Dijk, Richard P...
DAC
1997
ACM
13 years 10 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
13 years 11 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
DAC
2006
ACM
14 years 6 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...
NAR
2007
132views more  NAR 2007»
13 years 5 months ago
Expanded protein information at SGD: new pages and proteome browser
The recent explosion in protein data generated from both directed small-scale studies and largescale proteomics efforts has greatly expanded the quantity of available protein info...
Robert S. Nash, Shuai Weng, Benjamin C. Hitz, Rama...