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» Incremental formal design verification
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ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
13 years 9 months ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton
IJCAI
2003
13 years 6 months ago
Formal Verification of Diagnosability via Symbolic Model Checking
This paper addresses the formal verification of diagnosis systems. We tackle the problem of diagnosability: given a partially observable dynamic system, and a diagnosis system obs...
Alessandro Cimatti, Charles Pecheur, Roberto Cavad...
VLSID
2008
IEEE
225views VLSI» more  VLSID 2008»
14 years 5 months ago
Formal Verification of a Public-Domain DDR2 Controller Design
This paper demonstrates a formal verificationplanning process and presents associated verification strategy that we believe is an essential (yet often neglected) step in an ASIC o...
Abhishek Datta, Vigyan Singhal
CAV
1998
Springer
86views Hardware» more  CAV 1998»
13 years 9 months ago
Formal Verification of Out-of-Order Execution Using Incremental Flushing
We present a two-part approach for verifying out-of-order execution. First, the complexity of out-of-order issue and scheduling is handled by creating der abstraction of the out-of...
Jens U. Skakkebæk, Robert B. Jones, David L....
ICCAD
2007
IEEE
102views Hardware» more  ICCAD 2007»
14 years 1 months ago
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1, …, gn}, i.e. f = h(g1, …, gn). It plays an important r...
Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang H...