3 search results - page 1 / 1 » Incremental retiming for FPGA physical synthesis |
DAC
2005
ACM
14 years 5 months ago
2005
ACM
In this paper, we present a new linear-time retiming algorithm that produces near-optimal results. Our implementation is specifically targeted at Altera's Stratix [1] FPGAbas...
TODAES
2008
13 years 4 months ago
2008
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...