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» Inductance Aware Interconnect Scaling
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DATE
2005
IEEE
108views Hardware» more  DATE 2005»
13 years 11 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
SIGCOMM
2012
ACM
11 years 8 months ago
On-chip networks from a networking perspective: congestion and scalability in many-core interconnects
In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting similarities and differences between the two. As an initial case...
George Nychis, Chris Fallin, Thomas Moscibroda, On...
VLDB
2007
ACM
115views Database» more  VLDB 2007»
14 years 6 months ago
Context-Aware Wrapping: Synchronized Data Extraction
The deep Web presents a pressing need for integrating large numbers of dynamically evolving data sources. To be more automatic yet accurate in building an integration system, we o...
Shui-Lung Chuang, Kevin Chen-Chuan Chang, ChengXia...
ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
14 years 4 days ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...
CODES
2006
IEEE
13 years 11 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha