Sciweavers

1192 search results - page 1 / 239
» Instruction Level Distributed Processing
Sort
View
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
13 years 9 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
HIPC
2000
Springer
13 years 8 months ago
Instruction Level Distributed Processing
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
James E. Smith
IPPS
2000
IEEE
13 years 8 months ago
MAJC-5200: A High Performance Microprocessor for Multimedia Computing
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
Subramania Sudharsanan
MICRO
1998
IEEE
108views Hardware» more  MICRO 1998»
13 years 8 months ago
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...
Chia-Lin Yang, Barton Sano, Alvin R. Lebeck