Sciweavers

15 search results - page 3 / 3
» Instruction Wake-Up in Wide Issue Superscalars
Sort
View
ICCD
2004
IEEE
104views Hardware» more  ICCD 2004»
14 years 3 months ago
Exploiting Quiescent States in Register Lifetime
Large register file with multiple ports, but with a minimal access time, is a critical component in a superscalar processor. Analysis of the lifetime of a logical to physical reg...
Rama Sangireddy, Arun K. Somani
IPPS
2005
IEEE
13 years 12 months ago
A Dependency Chain Clustered Microarchitecture
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...
Satish Narayanasamy, Hong Wang 0003, Perry H. Wang...
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
13 years 10 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
13 years 6 months ago
Speculative Dynamic Vectorization
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
Alex Pajuelo, Antonio González, Mateo Valer...
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
13 years 11 months ago
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor
This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressiv...
André Seznec, Stephen Felix, Venkata Krishn...