369 search results - page 1 / 74 » Instruction set mapping for performance optimization |
ICCAD
1993
IEEE
13 years 8 months ago
1993
IEEE
DAC
2003
ACM
13 years 10 months ago
2003
ACM
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...
ASPDAC
2009
ACM
13 years 5 months ago
2009
ACM
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations a...
ISSS
1997
IEEE
13 years 8 months ago
1997
IEEE
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
IEEEPACT
2002
IEEE
13 years 9 months ago
2002
IEEE
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...