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VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
14 years 5 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski
VLSI
2012
Springer
12 years 16 days ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 5 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
EVOW
2003
Springer
13 years 10 months ago
Genophone: Evolving Sounds and Integral Performance Parameter Mappings
This paper explores the application of evolutionary techniques to the design of novel sounds and their characteristics during performance. It is based on the “selective breeding...
James Mandelis
CASES
2003
ACM
13 years 8 months ago
A hierarchical approach for energy efficient application design using heterogeneous embedded systems
Several features such as reconfiguration, voltage and frequency scaling, low-power operating states, duty-cycling, etc. are exploited for latency and energy efficient application ...
Sumit Mohanty, Viktor K. Prasanna