860 search results - page 1 / 172 » Integration of VHDL into a system design environment |
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
Verification of image processing systems is mainly done on the basis of image sequence simulations. To achieve high simulation efficiency, our compiled code simulator MSIPC offers...
ARC
2010
Springer
13 years 5 months ago
2010
Springer
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
This paper presents a new concept for accurate modeling and timing simulationof electronicsystems integrated in a typical VHDL design environment, taking into account the requirem...
12
Voted
EUROMICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
DPLAYOUT is a layout synthesis tool for bit-sliced datapath designs targeting standard-cell libraries. We developed fast and efficient heuristics for placing the cells in a bit-s...