Integration of VHDL into a system design environment

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Verification of image processing systems is mainly done on the basis of image sequence simulations. To achieve high simulation efficiency, our compiled code simulator MSIPC offers a high performance clock period precision simulation, according to the SDF simulation paradigm. Furthermore it supports mixed mode (e.g. VHDL) simulations via coupling to external simulators, and via cross-compiling.

Ludwig Schwoerer, Matthias Lück, Hartmut Schr

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EURODAC 1995 | Image Sequence Simulations | Period Precision Simulation | SDF Simulation Paradigm | VHDL |

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Added	26 Aug 2010
Updated	26 Aug 2010
Type	Conference
Year	1995
Where	EURODAC
Authors	Ludwig Schwoerer, Matthias Lück, Hartmut Schröder

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Integration of VHDL into a system design environment

EURODAC 1995 | Image Sequence Simulations | Period Precision Simulation | SDF Simulation Paradigm | VHDL |

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