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» Integration of VHDL into a system design environment
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DATE
1999
IEEE
95views Hardware» more  DATE 1999»
13 years 9 months ago
Object-Oriented Reuse Methodology for VHDL
In the reuse domain, the necessity of finding a new, more suitable description language opposes the need to make reuse an accepted practice, and thus related to standards. This pa...
Cristina Barna, Wolfgang Rosenstiel
WCE
2007
13 years 6 months ago
Secure Multicarrier Modem on FPGA
— The paper deals with the design and realization of a secure multicarrier modem on FPGA. The crypto-modem principle is adopted. An encryption block is integrated in the modem tr...
Galia Marinova, Vassil Guliashki, Didier Le Ruyet,...
EURODAC
1994
IEEE
149views VHDL» more  EURODAC 1994»
13 years 9 months ago
A Graphical Approach to Analogue Behavioural Modelling
In order to master the growing complexity of analogue electronic systems, modelling and simulation of analogue hardware at various levels is absolutely necessary. This paper prese...
Vincent Moser, Pascal Nussbaum, Hans Peter Amann, ...
EURODAC
1995
IEEE
138views VHDL» more  EURODAC 1995»
13 years 8 months ago
Reduced design time by load distribution with CAD framework methodology information
This paper is focused on reducing the design time in a CAD framework environment by the optimal use of resources. A user-transparent load distribution system (Framework based LOad...
Jürgen Schubert, Arno Kunzmann, Wolfgang Rose...
DATE
2009
IEEE
136views Hardware» more  DATE 2009»
14 years 21 hour ago
A novel approach to entirely integrate Virtual Test into test development flow
– In this paper, we present an open architecture Virtual Test Environment (VTE) which can be easily integrated into various modularized Automatic Test Systems (ATS) compliant to ...
Ping Lu, Daniel Glaser, Gürkan Uygur, Klaus H...